Along with development of the digital technology, recent years have seen a further increase in functionality of electronic devices such as mobile information devices and information home appliances. Accordingly, there is an increasing demand for a nonvolatile memory device with a higher capacity, lower power consumption for writing, a higher speed of reading/writing, and a longer product lifetime.
In response to such a demand, an attempt to downsize a flash memory which includes an existing floating gate is under way.
Meanwhile, research and development have been directed toward, as an element which replaces the flash memory, a nonvolatile memory device which includes a memory element configured using what is called a variable resistance memory element. The variable resistance memory element indicates an element which has a resistance value changing according to electrical signals, has properties of keeping the resistance value even when the electrical signals are no longer supplied (that is, keeping the resistance value in a nonvolatile manner), and is capable of storing data using a change in this resistance value.
Representative examples of the variable resistance memory element include a magnetic random access memory (MRAM), a phase change random access memory (PRAM), a resistance random access memory (ReRAM; a variable resistance element), a spin transfer torque random access memory (SPRAM), and a conductive bridge random access memory (CBRAM).
As an example of the structures of the nonvolatile memory devices which include these variable resistance memory elements, a cross-point structure is known. In the cross-point structure, memory cells are arranged each of which has two terminals and is located at a cross-point between a bit line and a word line that are perpendicular to each other; the memory cell is located between the bit line and the word line. The memory cell is configured with a memory element that includes a variable resistance memory element as its single element or includes a series-connected combination of a variable resistance memory element with a two-terminal switching element, such as a diode, such that the memory element has one electrode connected to the word line and the other electrode connected to the bit line. The cross-point structure is characterized by being suitable for large-scale integration as compared to what is called the 1T1R structure in which each variable resistance memory element is connected to a bit line via an access transistor having three terminals.
In the cross-point structure, the memory cells are arranged in an array (which is hereinafter referred to as a cross-point cell array). In the cross-point structure, to detect (read) a resistance value of a memory element included in a target memory cell, a voltage is applied to a corresponding set of the bit line and the word line, which causes a current to flow not only in the target memory cell, but also in the other memory cells which are connected in parallel by upper and lower bit and word lines. The current flowing across the other memory cells is called a sneak current herein. Since the sneak current changes depending on the condition of data stored in the cross-point cell array (the resistance values and its distribution of the memory elements included in all the memory cells within the cross-point cell array to which the target memory cell belongs), the current detected upon reading always includes offset current (that is a sneak current) of which a value is always not constant. This sneak current impairs accurate detecting of the resistance value of the memory element included in the target memory cell to be read.
By configuring the memory element in which the switching element and the variable resistance memory element are connected in series, this sneak current can be reduced to some extent. However, the sneak current increases according to the size of the cross-point cell array, which means that the sneak current is an impediment to the enlargement of the cross-point cell array.
Patent Literature (PTL) 1 discloses a memory device configured to reduce sneak current-induced sensitivity deterioration in detecting a resistance value of the memory element included in the memory cell.